Above: Dr. Sang-il Park, CEO and Founder of Park Systems shares his vision for the future of AFM technology for industrial nanometrology and the latest technological innovations from Park Systems at the Park AFM Luncheon. “Our partnership with many leading semiconductor institutions such as imec and Stanford provides a crucial link of scientific collaboration throughout the chain of suppliers and vendors in semiconductor wafer production creating significant technological advances in AFM-based inline nanoscale metrology,” stated Dr. Sang-il Park, CEO of Park Systems. “We were excited to showcase these advances at this year’s Semicon West show and give highlights at our AFM luncheon.”
Presentations by Dr. Sang-il Park, CEO of Park Systems and Prof. Saraswat, Stanford University
New Materials and Structures for Technology Progression in 3D Heterogeneous Integration of Semiconductor Devices
Q & A with Park Systems Research Scientist
Can you explain more about what 3D crystallization refers to in regards to ICS fabrication technology? How far in the future do you think it will be before this becomes more commonly used?
3D crystallization refers to a process where you take join a completed first level circuit and join it to a crystalline structure (e.g., another silicon wafer) that has been placed on top of it. This process is completed by using a technique like plasma-activated lower temperature wafer bonding. After completing a second level circuit on the newly placed crystalline structure through laser annealing, you could then add a third, fourth, etc. crystalline structure and continue building the IC vertically. This fabrication technology confers multiple benefits including reduced ICS power consumption, cost, and footprint, however, there are several challenges that need to be overcome before it becomes more commonly used. For starters, building up ICS systems vertically introduces cumulative heat buildup with each circuit level, the issue of trapped contamination between layers, and potential layer misalignment.
What are 3D self-assembled devices? Do you know where research on these type of devices is being performed?
3D self-assembled devices are created by influencing molecules to bind one another in large numbers to create 3D structures. This occurs all the time in biological processes and now we are applying research in related fields such as supramolecular chemistry to predict how and eventually get elements to self-assemble into structures useful for specific applications such as transistors on a semiconductor chip. Self-assembly is one of the holy grails of nanotechnology and is subsequently a very hot topic for research and industrial labs around the world to explore.
How will advances in 3D integration affect our technology? Can you give some examples of future products or technologies that do not exist now but may once we achieve heterogeneous 3D integration on silicon platforms?
3D integrated circuits are strongly considered to be answer to ever-growing market demands for continuously miniaturize and improve our electronics. As we select and optimize from the currently fragmented playing field of myriad 3D integration techniques, we should see next-generation tech products with greater storage capacity, lower power requirements, more efficient thermal designs, higher brightness and more vivid displays and lighting, and faster networking throughput than ever before. For example, currently, smart watches are generally positioned in the market as fitness trackers or complementary devices to more powerful mobile devices like smart phones due to the watches’ technical limitations. With advanced 3D integration capabilities, we may finally be able to untether next-generation smart watches and have them available as more stand-alone products than they currently are.
How is Park AFM (or just AFM in general) used to advance the emerging and future technologies for 3D heterogeneous integration? Does AFM play an important role in helping advance these technologies more quickly and why?
To perform the direct surface bonding of one wafer to another (as in 3D crystallization techniques), each of the wafers need to have exceptionally smooth surfaces with roughness values below 1 nm. Atomic force microscopy plays a significant role in obtaining surface roughness measurements of silicon wafers to be used in ICS fabrication.
Prof. Saraswat, the Rickey/Nielsen Professor in the School of Engineering at Stanford University gave an informational talk entitled, “Real Limits to Nanoelectronics: Interconnects and Contacts” to a standing room only crowd at the Park Systems Semicon West AFM luncheon July 11, 2017 about future high performance chips, the latest technology for optical interconnects and other interconnect innovations.
His research currently investigates new device structures to continue scaling MOST transistors, DRAMs and flash memories to the nanometer regime, 3-dimensional ICs with multiple layers of heterogeneous devices, metal and optical interconnections, and high efficiency and low cost solar cells.
REAL LIMITS TO NANOELECTRONICS: INTERCONNECTS AND CONTACTS
Modern electronics has advanced at a tremendous pace over the course of the last half century primarily due to enhanced performance of MOS transistors due to dimension scaling. Silicon bulk CMOS dominated the microelectronics industry in the past. However, future Si technology is reaching practical and fundamental limits. To go beyond these limits FinFETs have been introduced and novel device structures like surround gate FETs, TunnelFETs, etc. and potentially higher performance material like Ge, III-Vs, carbon nanotubes and 2D materials are being aggressively studied.
As device scaling continues, parasitic source resistance largely dominated by contact resistance is beginning to limit the device performance. Historically the method to reduce ρ2is by increasing doping density thereby thinning the barrier, thus allowing more tunneling current. This method works well for n-Si and p-Ge which can be doped heavily. It is not very practical for n-Ge, p-Si, many III-Vs and 2D materials because of the inability to dope them heavily.
There are many other alternatives to reduce contact resistance, such as, metastable doping, Fermi level de-pinning and band engineered heterostructures.
While novel structures and materials have enhanced the transistor performance, the opposite is true for the interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on- chip applications. Many of these obstacles stem from the physical limitations of copper/low-k electrical wires, namely the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper and the dielectric capacitance.
Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. This talk will address effects of scaling on the performance of Cu/low-k interconnects, alternate interconnect schemes: carbon nanotubes (CNT), graphene, optical interconnect, three-dimensional (3-D) integration and heterogeneous integration of these technologies on the silicon platform.
About Prof. Krishna Saraswat
Prof. Krishna Saraswat is Rickey/Nielsen Professor in the School of Engineering, Professor of Electrical Engineering and by courtesy Professor of Materials Science & Engineering at Stanford University. He received Ph.D. from Stanford University and B.E. from BITS, Pilani, India. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. Prof. Saraswat has supervised more than 85 doctoral students, 25 postdoctoral scholars and has authored or co-authored 15 patents and over 750 technical papers, of which 10 have received Best Paper Award. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000, the 2004 IEEE Andrew Grove, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the Semiconductor Industry Association Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.